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CXD1913AQ
Digital Video Encoder
Description The CXD1913AQ is a digital video encoder designed for video CD, car navigation system and other digital video applications. The device accepts ITU-R601 compatible Y, Cb, Cr data and also accepts ITUR656-format Y, Cb, Cr data, and the data are encoded to composite video and separate Y/C video (S-Video) signal. Features * NTSC and PAL encoding mode * Composite video and separate Y/C video (S-Video) signal outputs * 8/16-bit pixel data input mode * 13.5 Mpps pixel rate * Interlace and non-interlace supported * On-chip 100% color bar generator * 10-bit 3 channels DACs * Supports I2C bus (400kHz) and SONY SIO * Closed Caption (Line 21, Line 284) encoding * VBID encoding * Monolithic CMOS single 3.3V 5% and 5.0V 5% power supplies * 64-pin plastic QFP package 64 pin QFP (Plastic)
Absolute Maximum Ratings -0.3 to +7.0 * Supply voltage VDD * Input voltage VI -0.3 to +7.0 * Output voltage VO -0.3 to +7.0 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -40 to +125 (Vss = 0V) Recommended Operating Conditions * Logic supply voltage DVDD 3.3V 5% DVDD * Analog supply voltage AVDD AVDD * Input voltage VIN * Operating temperature Topr I/O Capacitance * Input pin * Output pin 5.0V 5% 3.3V 5% 5.0V 5% Vss to VDD 0 to +70
V V V C C
V C
CI CO
11 (Max.) 11 (Max.)
pF pF
Note) Test conditions: VDD = VI = 0V fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97918-PS
Block Diagram
XTEST1 to 3 XTEST
37 to 39, 54
25 VB
PD0 to 7 Y Delay 10bit DAC
1 to 4, 6 to 9
29 Y-OUT
PD8 to 15 11 to 18 LPF
CHROMA
U Interpolator Modulator LPF
PDCLK 57
1/2
Demultiplex, Level Translator and interpolator 4:2:2 to 4:4:4 V
10bit DAC
24 COMP-O
10bit DAC
32 C-OUT
SYSCLK 56 BURST FLAG CSYNC SYNC Slope Gen. Sub Carrier Gen. 20 IREF 21 VREF 26 VG
-2-
Closed Caption Encoder (for NTSC) VBID Encoder (for NTSC)
VSYNC 59
HSYNC 60
FID 62
XVRST 51
SYNC Gen. and Timing Controller
F1/XTEST4 52
SI/SDA 48 46 TDO 43 TDI 44 TMS 45 TCK 41 TRST
SCK/SCL 49
XCS/SA 50
SIO Controller
SO 61
XIICEN 64
XRST 55
CXD1913AQ
CXD1913AQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol PD7 PD6 PD5 PD4 VSS PD3 PD2 PD1 PD0 VDD PD15/TD7 PD14/TD6 PD13/TD5 PD12/TD4 PD11/TD3 PD10/TD2 PD9/TD1 PD8/TD0 VSS IREF VREF AVDD1 AVSS1 COMP-O VB VG AVDD2 AVSS2 Y-OUT AVDD3 AVSS3 I/O I I I I -- I I I I -- I/O I/O I/O I/O I/O I/O I/O I/O -- O I -- -- O O O -- -- O -- -- Digital ground Reference current output. Connect resistance "16R" which is 16 times output resistance "R". Voltage reference input. Sets output full scale value. Analog power supply Analog ground 10-bit D/A converter output. This pin outputs composite signal. Connect to VSS with a capacitor of approximately 0.1F. Connect to AVDD with a capacitor of approximately 0.1F. Analog power supply Analog ground 10-bit D/A converter output. This pin outputs luminance (Y) signal. Analog power supply Analog ground 8-bit pixel data input pins / Test data bus. When control register bit "PIF MODE" = "0": These inputs are not used. When control register bit "PIF MODE" = "1": These are inputs for multiplexed Cb and Cr signal. For test mode, it's used for internal circuit test data bus. Test mode is available only for device bender. Description 8-bit pixel data input pins (PD0 to 7). When control register bit "PIF MODE" = "0": These are inputs for multiplexed Y, Cb, and Cr signal. When control register bit "PIF MODE" = "1": These are inputs for Y signal. Digital ground 8-bit pixel data input pins (PD0 to 7). When control register bit "PIF MODE" = "0": These are inputs for multiplexed Y, Cb, and Cr signal. When control register bit "PIF MODE" = "1" These are inputs for Y signal. Digital power supply
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CXD1913AQ
Pin No. 32
Symbol C-OUT
I/O O
Description 10-bit D/A converter output. This pin outputs chroma (C) signal. Test data bus. This pin should be open. For test mode, it's used for internal circuit test data bus. Test mode is available only for device bender. Digital power supply Test data bus. These pins should be open. For test mode, it's used for internal circuit test data bus. Test mode is available only for device bender. Test mode control inputs. These pins are pulled up. Normally, these pins should be open. Digital ground Test mode reset input. This pin is pulled up. For power on reset, set "L" for more than 40 clocks (SYSCLK). Digital power supply Test mode control input. This pin is pulled up. Test mode control input. This pin is pulled up. Test mode control input. This pin should be "H" input. Test data bus output. This pin should be open. Digital ground This pin's function is selected by XIICEN (Pin 64). When XIICEN = "H", this pin is SONY SIO mode; SI serial data input. When XIICEN = "L", this pin is I2C bus mode; SDA input/output. This pin's function is selected by XIICEN (Pin 64). When XIICEN = "H", this pin is SONY SIO mode; SCK serial clock input. When XIICEN = "L", this pin is I2C bus mode; SCL input. This pin's function is selected by XIICEN (Pin 64). This pin is pulled up. When XIICEN = "H", this pin is SONY SIO mode; XCS chip select input. When XIICEN = "L", this pin is I2C bus mode; SA slave address select input signal which selects I2C bus slave address. Vertical sync reset input in active low. This pin is pulled up. This is used to synchronize external vertical sync and internal vertical sync. When XVRST is "L", internal digital sync generator is reset according to F1 status. Valid only for 8-bit mode (control register address 01H bit 4 "PF MODE" = "0"). This pin's function is selected by XTEST (Pin 54). When XTEST = "H", this pin is F1; field ID input. Field ID during vertical sync reset is indicated. "H" indicates 1st field. "L" indicates 2nd field. When XTEST = "L", XTEST4 input.
33
TD10
I/O
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
VDD TD9 TD8 XTEST1 XTEST2 XTEST3 VSS TRST VDD TDI TMS TCK TDO VSS SI/SDA
-- I/O I/O I I I -- I -- I I I O -- I
49
SCK/SCL
I
50
XCS/SA
I
51
XVRST
I
52
F1/ XTEST4
I
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CXD1913AQ
Pin No. 53 54 55 56
Symbol VDD XTEST XRST SYSCLK
I/O -- I I I Digital power supply
Function
Test mode control input. This pin is pulled up. Normally, this pin should be open. System reset input in active low. For power on reset, set "L" for more than 40 clocks (SYSCLK). System clock input. To generate correct subcarrier frequency, precise 27MHz is required. Pixel data clock output. This clock is divided in half from SYSCLK. This is used when 16-bit pixel data mode. Digital ground Vertical sync signal output. Horizontal sync signal output. This pin's function is selected by XIICEN (Pin 64). When XIICEN = "H", this pin is SONY SIO mode; SO serial out output. When XIICEN = "L", this pin is not used and output is high impedance. Field ID output. When control register bit "FIDS" = "1": "L" indicates 1st field, "H" indicates 2nd field. When control register bit "FIDS" = "0": "H" indicates 1st field, "L" indicates 2nd field. Digital power supply Serial interface mode select input. This pin is pulled up. When XIICEN = "L", Pins 48 to 50 and 61 are I2C bus mode. When XIICEN = "H", Pins 48 to 50 and 61 are SONY SIO mode.
57 58 59 60 61
PDCLK VSS VSYNC HSYNC SO
O -- O O O
62
FID
O
63 64
VDD XIICEN
-- I
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CXD1913AQ
Electrical Characteristics DC characteristics Item Input high voltage Input low voltage Input high voltage Input low voltage Input high voltage Input low voltage Symbol Measurement conditionsConditions VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VDD = 5.0V 5% VDD = 3.3V 5% VDD = 5.0V 5% VDD = 3.3V 5% VDD = 5.0V 5% VDD = 3.3V 5% VDD = 5.0V 5% VDD = 3.3V 5% VDD = 5.0V 5% VDD = 3.3V 5% VDD = 5.0V 5% VDD = 3.3V 5% IOH = -2.4mA VDD = 5.0V 5% VDD = 3.3V 5% IOL = 4.8mA VDD = 5.0V 5% VDD = 3.3V 5% IOH = -1.2mA VDD = 5.0V 5% VDD = 3.3V 5% IOL = 2.4mA VDD = 5.0V 5% VDD = 3.3V 5% VI = 0 to 5.25V VDD = 5.0V 5% VDD = 3.3V 5% VI = 0V VDD = 5.0V 5% VDD = 3.3V 5% VDD = 5.0V 5% VDD = 3.3V 5% -10 VDD - 0.8 VDD - 0.8 0.7VDD 0.3VDD 2.4 1.8 0.8 0.5 Min. 2.2 1.8 0.8 0.5 (Ta = 0 to +70C, Vss = 0V) Typ. Max. Unit Pins V V V V V V 1 1 2 2 3 3 4
Output high voltage
VOH1
V
Output low voltage
VOL1
0.4
V
4
Output high voltage
VOH2
V
5
Output low voltage
VOL2
0.4
V
5
Input leak current
IIL1
10
A
6
Input leak current
IIL2
-40 -12
-100 -30
Supply current 1 2 3 4 5 6 7 8
IDD
-240 -75 70 8 40 8
A
7
mA
PD0 to 15, TD8 to 10, XTEST1 to 3, TRST, TDI, TCK, XCS/SA, XVRST, F1/XTEST4, XTEST, XRST, XIICEN SYSCLK SI/SDA, SCK/SCL PDCLK, VSYNC, HSYNC, FID, SO TDO, TD0 to 10 PD0 to 15, TD8 to 10, TCK, SI/SDA, SCK/SCL, F1/XTEST4, XRST, SYSCLK XTEST1 to 3, TRST, TDI, TMS, XCS/SA, XVRST, XTEST, XIICEN Not include analog current
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CXD1913AQ
DAC characteristics 1 Item Resolution Linearity error Differential linearity error Output full-scale current Output offset voltage Output full-scale voltage Precision guaranteed output voltage range Symbol n EL ED IFS VOS VFS VOC
(AVDD = 5.0V, R = 200, VREF = 2.0V, Ta = 25C) Measurement conditions Min. Typ. 10 -2.0 -1.0 9.5 10.0 2.0 1.0 10.5 1 1.9 1.9 2.0 2.0 2.1 2.1 Max. Unit bit LSB LSB mA mV V V
DAC characteristics 2 Item Resolution Linearity error Differential linearity error Output full-scale current Output offset voltage Output full-scale voltage Precision guaranteed output voltage range Symbol n EL ED IFS VOS VFS VOC
(AVDD = 3.3V, R = 200, VREF = 1.35V, Ta = 25C) Measurement conditions Min. Typ. 10 -3.0 -1.5 6.25 6.75 3.0 1.5 7.25 1 1.25 1.25 1.35 1.35 1.45 1.45 Max. Unit bit LSB LSB mA mV V V
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CXD1913AQ
AC characteristics 1. Pixel Data Interface (1) 8-bit mode
SYSCLK tPDS tPDH
PD0 to 7
(Ta = 0 to +70C, VDD = 3.3V 5%, 5.0V 5%, Vss = 0V) Item Pixel data setup time to SYSCLK Pixel data hold time to SYSCLK Symbol Min. 10 3 Typ. Max. Unit ns ns
tPDS tPDH
(2) 16-bit mode
PDCLK tPDS tPDH
PD0 to 15
(Ta = 0 to +70C, VDD = 3.3V 5%, 5.0V 5%, Vss = 0V) Item Pixel data setup time to PDCLK Pixel data hold time to PDCLK Symbol Min. 20 0 Typ. Max. Unit ns ns
tPDS tPDH
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CXD1913AQ
2. Serial Port Interface
fSCK tPWLSCK SCK tCSS XCS tSIS SI tSOD SO tSOH tSIH tCSH tPWHSCK
(Ta = 0 to +70C, VDD = 5.0V 5%, Vss = 0V) Item SCK clock rate SCK pulse width Low SCK pulse width High Chip select setup time to SCK Chip select hold time to SCK Serial input setup time to SCK Serial input hold time to SCK Serial output delay time from SCK Serial output hold time from SCK Symbol fSCK Min. DC 100 100 150 150 50 10 30 3 Typ. Max. 3 Unit MHz ns ns ns ns ns ns ns ns CL = 35pF
tPWLSCK tPWHSCK tCSS tCSH tSIS tSIH tSOD tSOH
(Ta = 0 to +70C, VDD = 3.3V 5%, Vss = 0V) Item SCK clock rate SCK pulse width Low SCK pulse width High Chip select setup time to SCK Chip select hold time to SCK Serial input setup time to SCK Serial input hold time to SCK Serial output delay time from SCK Serial output hold time from SCK Symbol fSCK Min. DC 100 100 150 150 50 10 50 3 Typ. Max. 3 Unit MHz ns ns ns ns ns ns ns ns CL = 35pF -9-
tPWLSCK tPWHSCK tCSS tCSH tSIS tSIH tSOD tSOH
CXD1913AQ
3. XVRST, F1
SYSCLK
tVS XVRST F1
tVH
(Ta = 0 to +70C, VDD = 3.3V 5%, 5.0V 5%, Vss = 0V) Item XVRST setup time to SYSCLK XVRST hold time to SYSCLK Symbol Min. 20 0 Typ. Max. Unit ns ns
tVS tVH
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID
fSYSCLK tPWHCLK tPWLCLK
SYSCLK
tPDCLKD PDCLK tCOD VSYNC, HSYNC, FID tCOH
tPDCLKD
(Ta = 0 to +70C, VDD = 5.0V 5%, Vss = 0V) Item SYSCLK clock rate SYSCLK pulse width Low SYSCLK pulse width High PDCLK delay time from SYSCLK Control output delay time from SYSCLK Control output hold time from SYSCLK Symbol fSYSCLK Min. Typ. 27 11 11 15 20 3 Max. Unit MHz ns ns ns ns ns CL = 35pF
tPWLCLK tPWHCLK tPDCLKD tCOD tCOH
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CXD1913AQ
(Ta = 0 to +70C, VDD = 3.3V 5%, Vss = 0V) Item SYSCLK clock rate SYSCLK pulse width Low SYSCLK pulse width High PDCLK delay time from SYSCLK Control output delay time from SYSCLK Control output hold time from SYSCLK Symbol fSYSCLK Min. Typ. 27 11 11 23 25 3 Max. Unit MHz ns ns ns ns ns CL = 35pF
tPWLCLK tPWHCLK tPDCLKD tCOD tCOH
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CXD1913AQ
Description of Functions The CXD1913AQ converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A) or PAL (ITU-R624; B, G, H, I) format. The CXD1913AQ first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts Cb and Cr signals into U and V signals respectively, interpolates 4:2:2 to 4:4:4, and modulates the signals with the subcarrier generated by digital subcarrier generator. Y signal and modulated chroma signal are oversampled (at double) to reduce sin (x)/(x) rolloff. 10-bit DACs are used for converting digital composite and Y/C signals into analog signals. 1. Pixel Input Format Pixel input format is determined by Bit 4 (PIF MODE) of control register address 01H as shown in Table 1-1. When PIF MODE is "0", the image data (Y, Cb, Cr) input from PD0 to PD7 is sampled at the rising edge of SYSCLK. When PIF MODE is "1", Y data is input into PD0 to 7, multiplexed Cb and Cr data are input into PD8 to 15, and these respective data are sampled at the rising edge of PDCLK. Table 1-1 PIF MODE 0 (8-bit mode) 1 (16-bit mode) PD15 to 8 NA Cb/Cr PD7 to 0 Y/Cb/Cr Y
Also, pixel input data sampling point is determined by Bits 3 and 2 (PIX TIM) of control register address 01H as shown in Table 1-2. During 8-bit mode, the data, which is sampled at the timing phase (Fig 1-1: 8-bit mode #0 to #3) set at PIX TIM from the falling edge of HSYNC, is recognized as Cb0. (in the default, the data, which is sampled at the rising edge of second SYSCLK from the falling edge of HSYNC), is recognized as Cb0. During 16-bit mode, the data, which is sampled at the timing phase (Fig 1-1: 16-bit mode #0 to #3) set at PIX TIM from the falling edge of HSYNC, is recognized as Cb0. (In the default, the data, which is sampled at the rising edge of second PDCLK from the falling edge of HSYNC), is recognized as Cb0. Table 1-2 PIX TIM 0 0 1 1 0 1 0 1 Timing phase #0 (default) #1 #2 #3
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CXD1913AQ
Pixel Data Input Timing
1 SYSCLK
2
3
4
5
1 PDCLK HSYNC
2
3
[16-bit mode] PD0 to 7 #0 PD8 to 15 #1 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Y0 Y1 Y2 Y3 Y4 Y5
Y0 #2 #3 Cb0
Y1 Cr0
Y2 Cb2
Y3 Cr2
Y4 Cb4
[8-bit mode] PD0 to 7 #0 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb2 Cb4 Y4 Cr4 Y5 Cb6
#1
Cb0
Y0
Cr0
Y1
Y2
Cr2
Y3
Cb4
Y4
#2 Cb0
Cb0
Y0
Cr0
Y1
Cb2
Y2 Cr2
Cr2
Y3
Cb4
Y4 Cr4
Cr4
#3
Y0
Cr0
Y1
Cb2
Y2
Y3
Cb4
Y4
Y5
PD0 PD1 : PD7
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
PD8 PD9 : PD15
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
Fig 1-1
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CXD1913AQ
2. Serial Interface The CXD1913AQ supports both I2C bus (high-speed mode) and Sony serial interface. These modes can be selected by XIICEN input pin as shown in Table 2-1 below. Table 2-1 XIICEN SI/SDA SCK/SCL XCS/SA SO H Sony SIO mode SI SCK XCS SO I2C L mode
SDA SCL SA Hi-Z
2-1. I2C bus interface The CXD1913AQ becomes a slave transceiver of I2C bus, and supports the 7-bit slave address and the highspeed mode (400K bit/s). 2-1-1. Slave address Two kinds of slave addresses (88H, 8CH) can be selected by the SA signal, as shown in Table 2-2 below. Table 2-2 A6 1 A5 0 A4 0 A3 0 A2 1 A1 SA A0 0 R/W X
2-1-2. Write cycle
S
slave address
W "0"
A
start address
A
write data
A
write data
A
P
from master to slave from slave to master
D7 start address
D6
D5
D4
D3
D2
D1
D0
ADR [4 : 0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start address register of this IC as start address of the control register. In subsequent cycles, the data supplied from the master is written in the addresses indicated by the control register address. The set control register address is automatically incremented with the completed transfer of each byte of data.
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CXD1913AQ
2-1-3. Read cycle
S
slave address
R "1"
A
read data
A
read data
A
P
from master to slave from slave to master
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and only ID code (addresses 09H, 0AH) is read out. During the read cycle, the start address is automatically set to 09H. Note) In the Sony SIO mode, addresses from 00H to 0AH can be read out. 2-1-4. Handling of general call address (00H) General call address is neglected and there is no ACK response.
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CXD1913AQ
2-2. Sony serial interface Sony serial interface uses SCK, XCS, SI and SO signals. Serial interface is activated when XCS signal is "Low", and samples serial input data at the rising edge of SCK. The first one byte after XCS activation is set up as a serial control command. The data includes a start control register address and direction of the serial interface. The control register address is automatically incremented with the transfer of each byte of data. In the write mode, the data of second byte and after are written in the addresses indicated by the address generated by the address generator of the CXD1913AQ. In the read mode, the serial input data is neglected and writing is not done. Serial Interface Timing
SCK XCS SI SO D0 LSB D1 D2 D3 D4 D5 D6 D7 MSB D0 LSB D0 D1 D2 D1 D2 D3 D4 D5 D6 D7 MSB D5 D6 D7
Serial control command
Serial data D3 D4
Serial Interface Sequence
SCK XCS SI Internl address generator 00H FFH 00H 11H 01H CEH 02H
Start control register address set Control register address auto-increment Control register address 00H 01H 02H Control register data FFH 11H CEH
Control register address auto-increment
2-1. Serial control command format D7 WR WR D6 D5 D4 D3 D2 D1 D0
ADR [4 : 0] : Direction for serial interface When this bit is "1": The serial interface is write mode. Incoming serial data is set up inside the control register according to the control register address. When this bit is "0": The serial interface is read mode. The control register data is output to SO according to the control register address.
ADR [4 : 0] : Start control register address - 16 -
CXD1913AQ
3. XVRST, F1 XVRST and F1 signals are used to synchronize with external V sync. XVRST and F1 signals are sampled at the rising edge of SYSCLK in 8-bit mode. F1 signal is sampled when XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it is reset to the 2nd field. When XVRST is set at High, digital sync generator starts operation, and the sequence of 1st or 2nd field starts.
In 8bit mode XVRST Timing (1st Field)
SYSCLK
XVRST
F1 "H" Start of 1st field (NTSC: 4H) (PAL: 1H)
VSYNC F-ID HSYNC
XVRST Timing (2nd Field)
SYSCLK
XVRST
F1 "L" Start of 2nd field (NTSC: 266H) (PAL: 313H) VSYNC F-ID 1/2H HSYNC
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CXD1913AQ
4. Closed Caption The CXD1913AQ supports closed caption encoding. ASCII data for closed caption encodes line 21 and line 284 by adding parity bit to ASCII data (data #1 and data #2 for line 21, data #1 and data #2 for line 284) which is set up for control registers 03H, 04H, 05H and 06H. Control registers 03H to 06H are double-buffered and ASCII data which is set up by serial interface is synchronized with VSYNC. ASCII data reset ON/OFF can be selected in synchronized with VSYNC by setting control register address 02H bit (OOEN). When OOEN = "1", the first stage buffer ASCII data is cleared at the rising edge of the field in the next VSYNC where data renewed. When OOEN = "0" (default), closed caption data is maintained. Closed Caption Data Renewal Timing
OOEN = "1" Field 4 FIELD 1 FIELD
VSYNC Control resisters 03H and 04H set SI/SDA Data 21H first stage buffer Data 21H last stage buffer Data 284H first stage buffer Data 284H last stage buffer DATA A NEW DATA
OLD DATA OLD DATA
NEW DATA
(7'h00) NEW DATA
DATA RESET (7'h00)
DATA A
(7'h00)
Field
1 FIELD
2 FIELD
VSYNC Control resisters 05H and 06H set SI/SDA Data 284H first stage buffer Data 284H last stage buffer Data 21H first stage buffer DATA A NEW DATA
OLD DATA
NEW DATA
(7'h00)
OLD DATA
NEW DATA
DATA RESET (7'h00)
Data 21H last stage bufer
DATA A
(7'h00)
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CXD1913AQ
OOEN = "0" Field 4 FIELD 1 FIELD
VSYNC Control register 03H and 04H set SI/SDA Data 21H first stage buffer Data 21H last stage buffer Data 284H first stage buffer Data 284H last stage buffer NEW DATA NEW DATA
OLD DATA OLD DATA
NEW DATA
DATA A
DATA A
Field
1 FIELD
2 FIELD
VSYNC Control register 05H and 06H set SI/SDA Data 284H first stage buffer Data 284H last stage buffer Data 21H first stage buffer Data 21H last stage buffer NEW DATA
OLD DATA
NEW DATA
OLD DATA
NEW DATA
DATA A
DATA A
Double Buffer for Closed Caption
SI/SDA 03H
VSYNC
Load
ASCII data #1
Closed Caption Signal Waveform
HSYNC Color burst Clock run-in Start bits ASCII data #1 ASCII data #2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
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CXD1913AQ
5. VBID (Video ID) The CXD1913AQ supports Video ID (Provisional standard of EIAJ, CPX-1204) encording to perform aspect ratio identification. VBID is 14-bit data as shown in Table 5-1, and adding 6-bit CRCC results total 20 bits. This data is put on 20H and 283H in the vertical blanking period of NTSC video signal. Encordes by adding CRCC to the VBID data which is set up for control registers 07H and 08H by serial interface. Control registers 07H and 08H are double-buffered and data which is set up by serial interface is synchronized with VSYNC. Table 5-1 bit-No. 1 2 3 4 5 6 4-bit width 4-bit width Contents Transmission aspect ratio Image display format Undefined
"1" Full mode (16:9) Letter box
"0" 4:3 Normal
A WORD 0 B WORD 1 WORD 2
Identification information for video and other signals (aural signal, etc.) which is propagated at the same with video Identification signal subordinated to WORD 0 Identification signal and information subordinated to WORD 0 (Provisional standard of EIAJ, CPX-1204)
VBID Double Buffer
SI/SDA 07H
VSYNC
Load
WORD 0
VBID Data Renewal Timing
VSYNC Control register 07H set SI/SDA NEW DATA
Data #1
OLD DATA
NEW DATA
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CXD1913AQ
VBID Code Layout 20-bit data is configured with WORD 0 = 6 bits; its contents are WORD 0-A = 3 bits and WORD 0-B = 3 bits. And 20-bit data, with WORD 1 = 4 bits, WORD 2 = 4 bits and CRC = 6 bits. bit 1 *** DATA 0-A WORD 0 6 bit 0-B WORD 1 4 bit WORD 2 4 bit CRC 6 bit *** bit 20
VBID Signal Waveform
IRE 100 Ref. bit 1 bit 2 bit 3 *** bit 20 70 IRE
0 2.235s 20ns -40 11.2s 0.6s 1H 49.1s 0.5s
0 IRE
6. Interlace and Non interlace Supported The CXD1913AQ can select interlace output or non interlace output by the set of Bit 1 (INTERLS) of control register address 01H. Register set value INTERLS 0 1 Number of lines/field Scan mode Non interlace Interlace NTSC 262 262.5 PAL 312 312.5
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NTSC Vertical Interval (Interlace)
Fields 1 and 3 Vertical blanking Vertical SYNC 3H Post-equalization 3H
Pre-equalization 3H
524
525
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
HSYNC
VSYNC
- 22 -
264 265 266 267 268 269 270 271 272 273 274
FID
Fields 2 and 4
261
262
263
282
283
284
285
HSYNC
VSYNC
FID
CXD1913AQ
PAL Vertical Interval (Interlace)
Fields 1 and 3 (1) 2.5H (3) (3) 2.5H 2.5H
(2)
(4)
(4)
620
621
622
623
624
625
1
2
3
4
5
6
7
8
20
21
22
23
24
HSYNC
VSYNC
- 23 -
Fields 2 and 4 (4) (2) (2) 311 312 313 314 315 316 317 318 319 320 321
FID
(1)
(3)
(3)
308
309
310
333
334
335
336
HSYNC
VSYNC
FID CXD1913AQ
NTSC Vertical Interval (Non interlace)
Field 1 1 Vertical blanking Vertical SYNC 3H 3H Post-equalization
Pre-equalization 3H
523
524
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
HSYNC
VSYNC
FID Field 2 1
- 24 -
264 265 266 267 268 269 270 271 272 273
261
262
263
281
282
283
284
285
HSYNC
VSYNC
FID
CXD1913AQ
1 "Field 1" or "Field 2" is used for the convenience of the description of frame.
PAL Vertical Interval (Non interlace)
Field 1 1
2H
2.5H
2.5H
620 623 624 1 2 3 4 5 6 7 8 20 21 22
621
622
23
24
HSYNC
VSYNC
FID
- 25 -
Field 2 1 2H 2.5H 2.5H 311 312 313 314 315 316 317 318 319 320
308
309
310
332
333
334
335
336
HSYNC
VSYNC
FID CXD1913AQ
1 "Field 1" or "Field 2" is used for the convenience of the description of frame.
CXD1913AQ
Vertical Synchronization Timing
0.148s 0.148s
2.3s
29.5s
27.1s 1/2H 63.555s
4.67s
NTSC Equalizing & Synchronizing Pulses
0.296s
0.296s
2.37s
29.63s
27.3s 1/2H 64s
4.67s
PAL Equalizing & Synchronizing Pulses
- 26 -
CXD1913AQ
Control Register Map In case "0" or "1" is indicated on the map below, fix that value. BIT Function Selection #1 7 Address 00H FIDS ENC MODE 6 MASK EN 5 PIX EN 4 1 3 CBAR 2 SET UP 1 0 0 ENC MODE R/W
Encoding mode 0 : PAL encoding mode 1 : NTSC encoding mode (Default) Set up enable 0 : Non set-up level, black = blanking level 1 : 7.5 IRE set-up level insertion (Default) Color bar enable 0 : on-chip color bar output enable (ITU-R100% color bar) 1 : on-chip color bar output disable (Default) When CBAR = "0", on-chip color bar generator is valid, and output is ITU-R100% color bar output. When CBAR = "1", input pixel data is valid, and output obeys input pixel data.
SET UP
CBAR
PIX EN
Pixel data enable 0 : Disable input pixel data 1 : Enable input pixel data (Default) When input pixel data is disabled, output becomes blanking level or black level regardless of input PD0 to PD15.
MASK EN
Mask enable 0 : When V-blanking, pixel data through 1 : When V-blanking, pixel data reject (Default) When MASK EN = "0", input pixel data during V-blanking interval are valid, and output obeys input pixel data. When MASK EN = "1", input pixel data during V-blanking interval are all invalid, and output becomes blanking level.
FIDS
FID polarity select 0 : 1st field "H", 2nd field "L" 1 : 1st field "L", 2nd field "H" (Default)
- 27 -
CXD1913AQ
BIT Function Selection #2 7 Address 01H 6 5 0 4 PIF MODE 3 PIX TIME 2 1 INTERLS 0 FREE RUN R/W
DAC MODE
FREE RUN
Free run 0 : SCH timing is reset every 4 fields for NTSC and every 8 fields for PAL (Default) 1 : No SCH timing reset Interlace 0 : Interlace (Default) 1 : Non interlace Pixel input timing (See the diagram on Page 13.) 0 0 : #0 (Default) 0 1 : #1 1 0 : #2 1 1 : #3 Pixel input format 0 : 8-bit mode Multiplexed Y, Cb, Cr (4:2:2) (Default) 1 : 16-bit mode Y and multiplexed Cb, Cr (4:2:2) DAC output activity 0 0 : Non-active 0 1 : Y-OUT and C-OUT active 1 0 : Comp-out active 1 1 : Both active (Default)
INTERLS
PIX TIME
PIF MODE
DAC MODE
- 28 -
CXD1913AQ
BIT Function Selection #3 7 Address 02H 0 6 0 5 0 4 0 3 VBID 2 OOEN 1 0 R/W
CC MODE
CC MODE
Closed caption encoding mode 0 0 : Disable closed caption encoding (Default) 0 1 : Enable encoding in 1st field (Line 21) 1 0 : Enable encoding in 2nd field (Line 284) 1 1 : Enable encoding in both fields Closed caption data reset 0 : Non reset (Default) 1 : Data reset synchronized with VSYNC VBID encode mode 0 : Disable encoding of VBID (Default) 1 : Enable encoding of VBID
OOEN
VBID
- 29 -
CXD1913AQ
BIT Closed Caption Character #1 for 21H 7 Address 03H Closed Caption Character #2 for 21H 7 Address 04H Closed Caption Character #1 for 284H 7 Address 05H Closed Caption Character #2 for 284H 7 Address 06H VBID#1 7 Address 07H 6 5 4 WORD 0-B 3 WORD 0 WORD 0-A 2 1 0 R/W 6 5 4 3 2 1 0 R/W 6 5 4 3 2 1 0 R/W 6 5 4 3 2 1 0 R/W 6 5 4 3 2 1 0 R/W
ASCII data #1
(Default: 0H)
ASCII data #2
(Default: 0H)
ASCII data #1
(Default: 0H)
ASCII data #2
(Default: 0H)
WORD 0-B VBID#2 7 Address 08H Device ID#1 7 Address 09H ID code Device ID#2 7 Address 0AH ID code 6 5 4 3 ID Code Identification Code: 19H 2 (Upper) 6 5 4 ID Code Identification Code: 13H 3 2 (Lower) 6 WORD 2 5 4 3 2 WORD 1
WORD 0-A
1
0 R/W
1 13H
0 RO
1 19H
0 RO
- 30 -
CXD1913AQ
Video Timing
MAGENTA
YELLOW
GREEN
WHITE
806
806 748 655 597 506 448 7.5 IRE 355 297
BLACK
CYAN
BLUE
RED
WHITE LEVEL
100 IRE
256 40 IRE 36
BLACK LEVEL BLANK LEVEL
SYNC LEVEL
NTSC Y (Luminance) Video Output Waveform
7.5 IRE SETUP
CYAN (320)
MAGENTA (299)
YELLOW (227)
GREEN (299)
RED (320)
BLUE (227)
832
622 20 IRE 512 402 COLOR BURST 192 BLANK LEVEL
NTSC C (Chroma) Video Output Waveform
7.5 IRE SETUP
- 31 -
BLACK
WHITE
CXD1913AQ
Video Timing
YELLOW
GREEN
MAGENTA
WHITE
806 806 744 643 580 100 IRE 482 419 318 256 40 IRE 36
BLACK
CYAN
BLUE
RED
WHITE LEVEL
BLANK LEVEL
SYNC LEVEL
NTSC Y (Luminance) Video Output Waveform No SETUP
YELLOW (245)
CYAN (347)
GREEN (324)
MAGENTA (324)
RED (347)
BLUE (245)
859
622 20 IRE 512 402 COLOR BURST 165 BLANK LEVEL
NTSC C (Chroma) Video Output Waveform No SETUP
WHITE
- 32 -
BLACK
CXD1913AQ
Video Timing
MAGENTA
YELLOW
GREEN
WHITE
806 806 744 643 580 100 IRE 482 419 318 256 43 IRE 20
RED
BLACK
CYAN
BLUE
WHITE LEVEL
BLANK LEVEL
SYNC LEVEL
PAL Y (Luminance) Video Output Waveform
MAGENTA (324)
YELLOW (245)
GREEN (324)
CYAN (347)
BLUE (245)
RED (347)
859
630 21.5 IRE 512 394 COLOR BURST 165 BLANK LEVEL
PAL C (Chroma) Video Output Waveform
WHITE
- 33 -
BLACK
CXD1913AQ
Interpolation Filter Characteristics
0
-10
Attenuation [dB]
-20
-30
-40
-50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Frequency [MHz]
Chrominance Filter Characteristics
0
-20
Attenuation [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 7 8 9 10 Frequency [MHz]
- 34 -
CXD1913AQ
Application Circuit 1
CXD1913AQ
AVDD VG 0.1F VREF 3.3k IREF AVSS 1k
Buff AMP COMP-O Y-OUT C-OUT VB 200 LPF 75
Video output
0.1F
VSS
Application Circuit 2
CXD1856Q (MPEG1 decoder) 8 Y 8 C PD8 to 15 PD0 to 7 CXD1913AQ (Video encoder)
FID
FID
HSYNC
HSYNC
VSYNC
VSYNC
DCLK
13.5MHz
PDCLK SYSCLK
27MHz Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 35 -
CXD1913AQ
Package Outline
Unit: mm
64PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 51 52 33 32
+ 0.1 0.15 - 0.05 0.15
+ 0.4 14.0 - 0.1
17.9 0.4
64 1 1.0 19
20
+ 0.2 0.1 - 0.05
0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 1.5g
- 36 -
0.8 0.2
+ 0.15 0.4 - 0.1
+ 0.35 2.75 - 0.15
16.3

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